To increase the degree of integration of LSIs, it is necessary to reduce the area occupied on the main surface of the substrate by the individual semiconductor elements which constitute an LSI.
FIG. 3(A) to 3(C) are schematic views illustrating a conventionally most widely known structure of MOS (Metal Oxide Semiconductor) type FET (hereinafter referred in some cases to simply as "MOSFET"). Namely, FIG. 3(A) is a plan view, as taken from above, of an essential portion of the semiconductor device; FIG. 3(B) is a sectional view taken along the one-dot chain line I--I of FIG. 3(A); and FIG. 3(C) is a sectional view taken along the one-dot chain line II--II of FIG. 3(A). In these Figures, only one element is shown and the hatching, etc. indicating sectional views are partially omitted. Further, in order to make it easier to understand the following descriptions, impurity diffusion regions for forming source and drain are referred as a "source region" and a "drain region" which are shown in a specified disposition relationship. However, this disposition relationship is only illustrative. Therefore, the function of the element is not impaired whatsoever even when the illustrated dispositions of the two regions have been reversed.
As well known, the MOSFET structure shown in these figures is the most basic structure among those of conventional elements, in which the voltage applied to a gate electrode 11 is used as a control signal for electrically switching a current passing between a source region 13 and a drain region 15.
First, as shown in FIG. 3(A), the gate electrode 11 is formed with a width W1 corresponding to disposition dimension of one element and is also formed with a length l1 in the shape of a stripe. Each element is electrically isolated from another by means of a field oxide film 17.
As shown in FIGS. 3(B) and 3(C), the element of this type uses a substrate 19 made of silicon, as a base layer, the above-mentioned gate electrode 11 being disposed on this substrate 19 via a gate insulating film 21. The above-mentioned source region 13 and drain region 15 are provided as independent constituent elements, respectively, on both sides of the gate electrode 11 (and the gate insulating film 21).
Usually, the gate length l1 is set at approximately 0.5 to 1.0 (.mu.m). Since the electric current passing between the source and the drain corresponding to the driving ability of the element is in proportional relation to the gate width W1, it is considered to be optimal that this width W1 is approximately ten times as large as the gate length l1, in consideration of the operating speed of the element. Accordingly, the width W1 is set at approximately 5 to 10 (.mu.m).
With an increase in the degree of integration of LSI, an attempt has been made to decrease the gate length l1 and the gate width W1. However, since both the l1 and W1 are set by utilizing the main surface of the substrate as the base layer in a two-dimensional manner, dimensional decreasing of the l1 and W1 is limited when considering that the above-mentioned driving ability and operating speed of the element should be maintained.
Under the above-mentioned existing circumstances, various proposals have been made as to the technology improving the degree of integration without impairing the function of the element. For instance, Japanese Laid Open Patent Publication No. 61-206253 discloses a technique enlarging the surface area effective to form the element by three-dimensional utilization of the base layer.
Another prior art technique disclosed in this publication will hereinafter be described with reference to the drawings.
FIG. 4 is a schematic perspective view of an essential portion of the element, which is intended to illustrate the above mentioned another prior art technique and in which hatching, etc. indicating sectional views are partially omitted. It is to be noted that FIG. 4 shows a structure of one MOSFET only although the above mentioned publication discloses a CMOS (Complementary MOS) in which two MOSFETs of different conductivity types are combined together into one device.
As will be seen in this FIG. 4, a difference in levels involving an upper main surface 23a, a wall surface 23b and a lower main surface 23c are formed in the substrate 19 in advance. The MOSFET is structured by utilizing this difference in levels. Usually, a groove or a trench formed in the main surface (corresponding to the upper main surface 23a) of the substrate 19 serving as the base layer is utilized for providing this difference in levels. The illustrated difference in levels is one of four levels which constitute such a groove. Accordingly, when forming a CMOS, a pair of opposing wall surfaces among a plurality of wall surfaces constituting the groove are utilized to form two MOSFETs, respectively.
To further explain the structure of the above-mentioned MOSFET, a gate insulating film 25 is formed on the wall surface 23b of the illustrated difference in levels. Further, a gate electrode 27 which is electrically isolated from the substrate 19 by the gate insulating film 25 is provided in such a manner as to diminish the difference in levels.
Furthermore, a source region 29 and a drain region 31 are formed in the substrate 19 in such a manner that respective diffusion depths thereof extend in a direction perpendicular to the wall surface 23b.
As will be seen in FIG. 4 as well, in case of this structure of the device, the gate width W2 is set in parallel with the main surface of the substrate, as in case of the device structure of which explanation has been made with reference to FIGS. 3(A) to 3(C).
On the other hand, the gate length 12 is set in a direction vertical to the main surface of the substrate by utilizing the above-mentioned difference in levels. For this reason, the wall surface 23b of the difference in levels is employed to form the element, so that it becomes possible to enlarge the surface area effectively.
However, in the above-mentioned prior art technique utilizing the difference in levels, the gate width W2 which necessitates approximately ten times larger size as the gate length l2 is set in parallel with the main surface of the substrate serving as the base layer, so that the effect of enlarging the surface area in a direction of thickness (direction vertical to the main surface) of the substrate by providing a difference in levels is relatively small, resulting in an insufficient increase in the degree of integration for FETs.
Besides, when studying the FET of FIG. 4 illustrated as a conventional structure from the standpoint of manufacturing process, there is a problem that, in the case of forming, by a conventionally most widely used ion implantation, the impurity diffusion regions used for forming source and drain such as the source region 29 and the drain region 31, performing of the process step involved becomes complicated.
In more detail, when performing ion implantation with respect to the upper main surface 23a, this surface 23a is damaged during the forming of the drain region 31 located deeply in the substrate 19 as the base layer.
Further, when forming the above-mentioned impurity diffusion regions by ion implantation with respect to the wall surface 23b from an oblique direction, it is necessary to form on the wall surface 23b an ion implantation mask extending in parallel with the main surface of the substrate. In case of the most typical element structure shown in FIGS. 3(A) to 3(C), the gate electrode is usually utilized for such a mask to form the impurity diffusion region by self alignment. In case of the element structure shown in FIG. 4, however, it is substantially difficult to form on the wall surface 23b a stripe-shaped mask extending in a direction parallel to the main surface. In addition, although the dimension of overlap region between the impurity diffusion region and the gate electrode needs to be controlled with high precision since the gate length decreases, it is impossible to control the dimension of overlap region vertically to the main surface.
Further, although no illustration is made in FIG. 4, when disposing electrodes, respectively, with respect to the two impurity diffusion regions for forming source and drain, the electrodes connected to the impurity diffusion regions formed in the substrate must be drawn out, respectively, through, for example, the groove formed in the lower main surface 23c in the vicinity thereof. Accordingly, in this electrode formation as well, a problem arises that the process step involved becomes complicated.
The object of the present invention, in view of the above-described conventional problems, is to provide the structure of a semiconductor element capable of improving the degree of integration of the field effect transistors by utilizing a difference in levels formed in the base layer, which can be realized by employing a simplified manufacturing process.